The present invention relates to a semiconductor device and, particularly, to a semiconductor device that generates a lower voltage potential.
For use in a semiconductor device, a circuit that generates a lower voltage potential which is used an internal power supply is widely known. For example, a regulator is described in Japanese Patent No. 2698702, wherein the regulator is able to positively prevent saturation of an output transistor and also prevents saturation of a transistor installed to prevent the saturation of the output transistor. Further, a semiconductor integrated circuit (IC) is described in Japanese Patent No. 3431446, wherein the IC is able to supply a stable internal lower voltage potential over a wide spectrum of voltages, independently of whether consumption current is large or small, when the IC is in either standby or active state, by selectively using one of two types of step-down circuits, as appropriate, depending on a voltage range.
FIG. 3 is a circuit diagram of a main section of a step-down circuit found in such patent documents as Japanese Patent No. 2698702 and Japanese Patent No. 3431446. In FIG. 3, an internal power supply generator 1 which is a step-down circuit is the circuit that uses a PMOS transistor as an element for outputting a lower voltage potential. This circuit comprises a PMOS transistor P1, an operational amplifier circuit OP1, and two resistor elements R1, R2.
Of the operational amplifier circuit OP1, a noninverting terminal (+) is coupled to a node VFB1, an inverting terminal (−) is coupled to a node VREF1, and an output terminal is coupled to a node VG1. Of the PMOS transistor P1, a source is coupled to a node VEXT which supplies an external power supply potential, a drain is coupled to a node VINT which generates a potential Vint which is an output voltage as an internal power supply for a load circuit, and a gate is coupled to the node VG1. A resistor element R1 is coupled between the node VINT and the node VFB1 and a resistor element R2 is coupled between the node VFB1 and a ground GND2. An intermediate potential produced by dividing the potential Vint by a resistance ratio between the resistor elements R1, R2 is supplied to the node VFB1. Further, an output terminal of a reference voltage generator 5 is coupled to the node VREF1 and a stable reference potential Vref1 is always supplied as long as an external power supply is on.
In the configuration as described above, the output node VG1 of the operational amplifier circuit OP1 stabilizes at a potential, as the potentials on the node VREF1 and the node VFB1 coupled to two input terminals of the operational amplifier circuit OP1 are equal. According to the potential on the output node VG1, a current that is supplied from the external power supply potential VEXT via the PMOS transistor P1 to the node VINT is determined. By this current, the potential Vint is determined. Here, if the load current at the node VINT increases and the potential Vint slightly decreases transiently, the potential on the node VFB1 also decreases slightly according to the resistance ratio between the resistor elements R1, R2. When the operational amplifier circuit OP1 detects a decrease in the potential on the node VFB1, it amplifies this difference and applies a feedback so that the potential on the node VG1 will decrease. As a result, the current supplied via the PMOS transistor P1 to the node VINT increases and the potential Vint recovers. By means of such a feedback path and by always monitoring the potential on the node VFB1, the node VINT is set at a predefined potential Vint.